1. Field of the Invention
The present invention relates to a gate driving circuit, and more particularly, to a high-reliability gate driving circuit having alternating pull-down mechanism.
2. Description of the Prior Art
Because the liquid crystal display (LCD) has advantages of thin appearance, low power consumption, and low radiation, the liquid crystal display has been widely applied in various electronic products for panel displaying. The operation of a liquid crystal display is featured by varying voltage drops between opposite sides of a liquid crystal layer for twisting the angles of the liquid crystal molecules in the liquid crystal layer so that the transmittance of the liquid crystal layer can be controlled for illustrating images with the aid of the light source provided by a backlight module.
In general, the liquid crystal display comprises a plurality of pixel units, a gate driving circuit, and a source driving circuit. The source driving circuit is utilized for providing a plurality of data signals to be written into the pixel units. The gate driving circuit comprises a plurality of shift register stages and functions to provide a plurality of gate driving signals for controlling related writing operations of the pixel units. That is, the gate driving circuit is a crucial device for providing a control of writing the data signals into the pixel units.
FIG. 1 is a schematic diagram showing a prior-art gate driving circuit. As shown in FIG. 1, for ease of explanation, the gate driving circuit 100 illustrates only a (N−1)th shift register stage 111, an Nth shift register stage 112, and a (N+1)th shift register stage 113. For sake of brevity, only the internal structure of the Nth shift register stage 112 is exemplified. The Nth shift register stage 112 is employed to generate a gate signal SGn according to a first clock CK1, a second clock CK2, and a gate signal SGn−1. The gate signal SGn is furnished to a corresponding pixel unit of a pixel array 101 via a gate line GLn so as to control a writing operation for writing the data signal of the data line DLi into the pixel unit. Furthermore, the gate signal SGn is forwarded to the (N+1)th shift register stage 113 and functions as a start pulse signal for activating the (N+1)th shift register stage 113. The Nth shift register stage 112 comprises a pull-up unit 120, an energy-store unit 135, a buffer unit 140, a pull-down unit 150, a discharging unit 155, and a control unit 160.
The energy store unit 135 is used to generate a driving control voltage VQn through performing a charging process based on the gate signal SGn−1 received by the buffer unit 140. The pull-up unit 120 is utilized for pulling up the gate signal SGn of the gate line GLn according to the driving control voltage VQn and the first clock CK1. The control unit 160 comprises a plurality of transistors for generating a control signal SCn based on the gate signal SGn−1 and the second clock CK2 having a phase opposite to the first clock CK1. The discharging unit 155 is utilized for pulling down the driving control voltage VQn to a low power voltage Vss by performing a discharging process on the energy-store unit 135 according to the control signal SCn. The pull-down unit 150 is employed to pull down the gate signal SGn to the low power voltage Vss based on the control signal SCn.
However, in the operation of the gate driving circuit 100, except for the interval during which the Nth shift register stage 112 is activated for generating the gate signal SGn having high voltage level, the control signal SCn holds high voltage level for enabling the pull-down unit 150 and the discharging unit 155. That is the transistors 151, 156 of the pull-down unit 150 and the discharging unit 155 maintain turn-on state in most of operating time, which is likely to incur an occurrence of threshold voltage drift and degrades the reliability and life-time of the gate driving circuit 100.